EDN

VHDL-200x improves design and verification productivity

VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market 1. Many users prefer VHDL for RTL design because the language continues to provide ...
EDN

DESIGN LANGUAGES: VHDL udpate safeguards IP

Santa Cruz, Calif. — Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week will announce it has approved a revised version of the VHDL ...
Design-Reuse

Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM

Henderson, NV – January 9, 2012 – Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), ...
Design-Reuse

Advancing VHDL's Verification Capabilities with VHDL-2019 Protected Types

The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification. Henderson, NV – ...
La Vanguardia

Circuit Design And Simulation With Vhdl

A presentation of circuit synthesis and circuit simulation using VHDL (including VHDL 2008), with an emphasis on design examples and laboratory exercises.This text offers a comprehensive treatment of ...
TechRepublic

Design of NoC Router Architecture Using VHDL

Network-on-Chip (NoC) is an advance design method of communication network into System-on-Chip (SoC). It provides solution to the problems of traditional bus-based SoC. It is widely considered that ...
TechRepublic

Design and Implementation of BPSK Modulator and Demodulator Using VHDL

In the last years, a major transition from analog to digital modulation techniques has occurred and it can be seen in all areas of wireless communication, satellite and cellular systems. This paper ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
Electronic Design

Accellera Okays VHDL 4.0

Based on feedback from trial implementations of VHDL 3.0, Accellera has approved VHDL 4.0, which addresses more than 90 issues discovered during the trial period for version 3.0. Based on feedback ...
Business Wire

Aldec and SynthWorks Deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the ...