Semiconductor Engineering

Things You Never Knew About System Verilog

System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005. Its ...
Electronics Weekly

Cadence schedules more ‘hands-on’ design training

Cadence is running a couple more ‘hands-on’ training sessions, relating to chip and PCB design, and system interconnect design. The courses are run at the Cadence UK training centre in Bracknell. * ...
EDN

Is there a Verilog or VHDL online course?

Hmmm, this is an interesting question. It all started with that Free Online FPGA Course I gave last week (you can access an archived version by Clicking Here). I just received an email from a guy who ...
Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...